Abstract
Studies of high-K CMOS process nodes in the context of future IC applications for ionizing environments
Alicja Michalowska-Forsyth1
1Institute of Electronics, Graz University of Technology
Abstract
With down-scaling of CMOS technologies the silicon dioxide gate in MOSFET has to be replaced with high dielectric constant (high-K) material. The insulator is thinner, resulting in lower density of gate leakage current. High-K materials are used in CMOS process nodes below 65 nm. Specifically the planar bulk processes 28 nm and 40 nm, relatively cheap comparing to FinFET or FDSOI, inevitably will gain on maturity over the coming years and will become more important in the future standard and custom integrated circuit solutions. Also applications designed for ionizing environments will want to benefit from the ultra-high speed offered by scaled processes. Consequently there is a great interest to better understand the effects of ionizing radiation on these IC fabrication processes. The results presented here as well as those found in the literature [1][2] point so far to a superior performance in terms of the total ionizing dose (TID) tolerance. Still, at high TID levels one can expect new effects in the electrical characteristics due to new wafer processing techniques during fabrication, changed doping profile and concentration [2], geometry constraints imposed by photolithography or device size shrinking that is not uniformly scaled vertically and horizontally [3]. Also related to novel material composition the previously neglected electron trapping has been reported in high-K gate stack devices [4][5]. This talk gives an outlook on the SIRENS (Studies of Ionizing Radiation Effects in NanoScale CMOS Technology Nodes) project, the first measurements, the scientific questions and on the future activities.
References
[1] Zhang, Chun-Min, et al. "Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm bulk MOSFETs." IEEE Transactions on Nuclear Science 2018, pp. 38-47.
[2] Bonaldo, Stefano, et al. "Influence of Halo Implantations on the Total Ionizing Dose Response of 28 nm pMOSFETs Irradiated to Ultrahigh Doses." IEEE Trans. on Nuclear Science 2018, pp. 82-90.
[3] Faccio, Federico, et al. "Influence of LDD Spacers and H+ Transport on the Total-Ionizing-Dose Response of 65-nm MOSFETs Irradiated to Ultrahigh Doses." IEEE Trans. Nucl. Sc. 2017, pp. 164-174.
[4] Zhou, X. J., et al. "Effects of Switched-Bias Annealing on Charge Trapping in HfO2 Gate Dielectrics." IEEE Transactions on Nuclear Science 53.6 (2006): 3636-3643.
[5] Dixit, Sriram K., et al. "Radiation Induced Charge Trapping in Ultrathin HfO2-Based MOSFETs." IEEE Transactions on Nuclear Science 54.6 (2007): 1883-1890.
Acknowledgments
The author gratefully acknowledges the contributions to the successful start of SIRENS project from Varvara Bezhenova and Nikolaus Czepl from Graz University of Technology. She is also thankful to Federico Faccio and Giulio Borghello from CERN for welcoming the team to join the experiments and for sharing the measurement data. The author is also grateful for the support of this research project by Field of Expertise “Advanced Materials Science” at Graz University of Technology as well as by Austrian Science Fund (FWF): P 33387-N.