Abstract

On-chip infrastructure to leverage system reliability for space applications

Fabian Vargas

IHP - Leibniz Institute for High Performance Microelectronics Germany
vargas@computer.org

 

Abstract

Technology scaling, which made electronics accessible and affordable for almost everyone on the globe, has advanced IC and electronics since sixties. Nevertheless, it is well recognized that such scaling has introduced new (and major) reliability challenges to the semiconductor industry.

This tutorial describes on-chip rad-hard infrastructure such as sensors, self-adaptive fault resilience control logic [1,2] and dedicated HW redundancy under development at IHP Microelectronics to detect and correct single-event transients (SETs) in logic and predict aging [3,4] during IC lifetime. Single-event upsets (SEUs) can be detected and corrected for memory elements placed in logic, and detected, corrected and predicted at certain conditions for errors in SRAM.

Currently, this on-chip infrastructure is being implemented by IHP in different versions of a quad-core RISC-V processor and a European multi-channel beamforming core-chip, whose general architectures will be briefly described. Both ICs have been designed by using a CMOS 130nm rad-hard technology developed at IHP. If available by the date of the symposium, a demonstrator of the developed RISC-V processor (either running in a FPGA or implemented in the ASIC) and experimental results will be presented and discussed as well.