Abstract

Exascale Reconfigurable and Rad-Hard Accelerated Computing in Space

Luca Sterpone¹, Andrea Portaluri¹, Eleonora Vacca¹, Giorgio Cora¹, Alp Kilic²

¹ Politecnico di Torino
² NanoXplore

 

Abstract

Radiation-hardened-by-design (RHBD) reconfigurable devices have gained a lot of attention thanks to their excellent compromise between costs and performance. Being of very limited use due to a lack of performance a few years ago, these devices are now capable of implementing a wide range of applications requiring high computational capabilities [1]. However, to further enhance computing capabilities and permit the effective implementation of Vision-Based Navigation (VBN) algorithms, an ad hoc HW accelerator able to elaborate multi-dimensional arrays (tensors) is needed [2]. Tensors are fundamental units to store data such as the weights of a node in a neural network. They perform basic math operations such as addition, elementwise multiplication, and matrix multiplication. This HW accelerator, defined as the Tensor Processing Unit (TPU), is an architecture customized for image elaboration algorithms and machine learning [3]. It can manage massive multiplications and additions at high speed with a limited design area and power consumption. Several design strategies investigated the efficient implementation of TPU on FPGA architectures by improving the pipeline strategy and resource sharing towards the TPU processing elements (PEs) or by unifying the tensor computation kernel. Nowadays, there are not any available design solutions for radiation-hardened TPU for FPGAs or ASICs having high performance and being radiation-hardened [4]. In this work, we present the first results achieved with an implementation of a TPU architecture on NG-Medium Radiation-Hardened FPGAs manufactured by NanoXplore. 
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References

[1]    A. Portaluri, S. Azimi and L. Sterpone, "Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs," 2023 22nd International Symposium on Parallel and Distributed Computing (ISPDC), Bucharest, Romania, 2023, pp. 16- 22, doi: 10.1109/ISPDC59212.2023.00023

[2]    L.Bozzoli et al., "EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications," 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6

[3]    E. Vacca, G. Ajmone and L. Sterpone, "RunSAFER: A Novel Runtime Fault Detection Approach for Systolic Array Accelerators," 2023 IEEE 41st International Conference on Computer Design (ICCD), Washington, DC, USA, 2023, pp. 596-604, doi: 10.1109/ICCD58817.2023.00095.

[4]    L. Sterpone, S. Azimi and C. D. Sio, "CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 4, pp. 1079-1092, April 2024

 

Acknowledgments

This work is supported by the ESA OSIP project TERRAC.